FPGA Based Speed Control of a Separately Excited DC Motor

ةردقب رمتسم رايت كرحم ةعرس يف مكحتلا مت 2 قيرط نع طاووليك هل راودلا ءزجلل ةيتلوفلا رييغت . عون نم ريغم قيرط نع زجنا راودلا ةيتلوف رييغت (Buck Regulator) . ريغملا اذه حيتافم يف مكحتلا مت دقو ةضبنلا ضرع نيمضت دلوم قيرط نع (PWM Generator) . مدختسا دقو (Series Compensator) يف مكحتلل ةقلغم ةرطيس ةراد يف يلاوتملا مكحتملا لمعلا ةرود (Duty Cycle) ضرع نيمضت دلومل ةضبنلا (PWM) . يداملا نايكلا فصو ةغل تدمتعأ (VHDL) نيمضت دلومو يلاوتملا مكحتملا ميمصت يف ةضبنلا ضرع . تراك مدختسأ (XILINX Spartan 3E) لع دمتعملا ايلقح ةجمربملا تاباوبلا ةرئاد ى

DC motors are widely used due to their performance. The starting torque, for example, in a DC motor can be higher several orders in magnitude than that for a comparable size AC motor; also DC motors can have a wide range of speed control and operate at speeds less or more than the rated speed. There are many applications of DC motors such as (automobiles, boats, computers, airplanes, traction motors, printers, subway trains, etc) [1,2]. The extensive usage of DC motors in different applications makes speed control of DC motors strongly needed.
DC-DC switching power converters, due to their high-efficiency, are essential parts of the power supply system in many electrical types of equipments [3]. From control point of view, operation of these converters can be considered as a tracking problem, where the output quantity (output voltage, Vo) is required to follow a reference command with low transient and steady state error. To control the armature voltage, a buck converter (step down converter) is used to vary the output voltage from zero to the supply voltage Vs (rated motor voltage).

Buck converter:
Choppers have several advantages such as high efficiency, control flexibility, light weight, small size, quick response, and regenerative braking down to low speeds [2,4]. Buck converter shown in Figure (1) is one kind of the DC to DC converters, which can vary the output voltage from zero to the supply voltage, and its can be explained into two function modes of operation: Mode one when the switch (S) is closed for a time (ton), the supply voltage will appear across the load resistance (R).
Mode two when the switch (S) is opened for a time (toff), the voltage across the load resistance (R) becomes zero. The following equation represents the average output voltage of the buck converter (Vo) [2]: ...(1) where: Vo : the output voltage, Vs : the supply voltage, K : duty cycle = ton /T , where (0≤ K ≤ 1), and T : the time of one cycle.   In general the buck converter is simple and needs a single transistor and it can produce an output voltage from 0 to Vs . The output voltage of a buck converter can be varied by varying the duty cycle in the PWM signal generator with fixed frequency.

Generating the PWM signal:
The PWM signal can be created by comparing a DC reference signal with a sawtooth carrier signal by using a comparator. In this work, a different approach is used to generate the PWM signal which is obtained digitally by using a programmable updown counter and the counter starts to count from a certain value (digital word) as shown in Figure ( The PWM output signal is generated periodically with a constant frequency. Sometimes this PWM signal is called Digital PWM (DPWM) [6]. This signal is generated by a VHDL code implemented in (Spartan 3E) FPGA. Figure (5) represents the flowchart of the PWM generator as implemented in (Spartan 3E) FPGA.

The controller (cascade compensator):
A general block diagram of the designed closed loop system is shown in Figure  (6). The controller section consists of a comparator and an up/down counter. The comparator is used to compare between the reference signal (Vref -8bits, coming from external 8-slide switches) and the feedback signal (Vtac -8bits, coming from ADC). If (Vref) is greater than (Vtac), the counter will count up. If it is less, then the counter will count down, while when (Vref) equals (Vtac), the counter will stay on its current value. The calculations for the output frequency (switching frequency) and the duty cycle depend on the number of counter bits (n). The following equations can be used for switching frequency calculations [5]: where: tsw : the switching time.
n : the number of counter bits. Tclk : the FPGA clock time period. fs : the switching frequency. K : the duty cycle. and Set point : digital word placed by external switches.

Figure (6): General block diagram for the system
In this work, a Xilinx (Spartan_3E) FPGA is used with clock frequency of (50MHz). To have a buck regulator switching frequency of about (3.051 kHz), an (14bit) up/down counter is implemented. Figure (7) shows the result of implementation of the code in FPGA with the help of (Xilinx ISE_9.2) simulator supplied by Xilinx.    When the motor parameters and the snubber circuit elements needed for the switch of the buck regulator were determined, a MATLAB model is designed by using semi power system blocks, and this model is shown in Figure (11) where it is used to check the results that have been obtained from the practical application.  Figure (14-a) shows MATLAB simulation at 1250 rpm with applied load 5 n.m, while Figure (14-b) gives motor speed response at 1250 rpm with applied load 5 n.m and with steady state error equals to (1.44%) as it is obtained from the DAQ also.

Conclusions:
Acceptable results were obtained from applying the cascade compensator controller. The steady state errors were being within the limits (of 5% criteria) [7], and for both opened and closed loop control systems. The following conclusions were obtained: 1-VHDL language makes the changes on the design easier to be carried out. 2-Changes on the design can be accomplished quickly and cheaply without need to change hardware components. 3-Implementation on FPGA and simulation by ISE-9.2 enabled us to check the results of the designed circuit before applying it to the motor. 4-Using the FPGA makes control of the switching frequency of the PWM output signal easier to vary; this can be accomplished by either changing the number of counter bits (n=14, in this work) or by changing the clock frequency.