Keywords : convention


Applying Standard JPEG 2000 Part One on Image Compression

Maha Abdul Rahman Hasso; Sahlah Abed Ali

AL-Rafidain Journal of Computer Sciences and Mathematics, 2020, Volume 14, Issue 1, Pages 13-33
DOI: 10.33899/csmj.2020.164796

In this paper, has been proposed Algorithm for standard JPEG2000 part one for image compression. The proposed Algorithm was executed by  using  MATLAB7.11  environment,  applied  these  algorithm  on  the gray and color images for type of the images natural, medical, Graphics images  and  remote  sensing.  Dependence  on  the  Peak  Signal-to-Noise Ratio  (PSNR)  for  comparing  the  result  of  the  proposed  Algorithm  by using the Daubechies filters 5/3 tap filter and 9/7 tap filter  Biothogonal , Another  comparison  is  held  concerning  the  obtained  results  of   the algorithm    of    ModJPEG  and  Color-SPECK. Proved  the  processing results Efficiency performance of   proposed Algorithm.
 

Representation of the Wavelet Transform 2D using A 5/3 Filter on the Field Programmable Gate Array

Maha Hasso; Sahla Abdul Ali

AL-Rafidain Journal of Computer Sciences and Mathematics, 2013, Volume 10, Issue 1, Pages 323-331
DOI: 10.33899/csmj.2013.163462

Recently the Wavelet Transform has gained a lot of   popularity in the field of signal and image processing, this is due to its capability of providing both time and frequency information simultaneously.In this paper, focus on used Discrete Wavelet Transform 2-dimenssion )2D- DWT) based on  conventional approach, convolution, to image processing and implementation by using FPGA(Field Programmable Gate Array) ,due to many researches were implemented on this Hardware in recent years ,using VHDL.
In this paper, has been proposed two VHDL architectures to implementation the conventional of the Daubechies 5/3-tap biorthogonal filter bank, a simple – straightforward one and an optimized one, substituting the multipliers used for scaling with shift – add operations. The architecture of optimized approaches were designed and implemented on FPGA, type of Xilinx XC3S500E Spartan-3E.